Silicon semiconductor technology has done marvels for the advancement of our society, which has benefited tremendously from its versatile use and amazing capabilities. The development of electronics, automation, computers, digital cameras and smartphones based on this material and its underpinning technology has reached skyrocket limits, downscaling the physical size of devices and wires to the nanometre regime.
Although this technology has been growing since the late 1960s, the miniaturization of circuits seems to have reached a possible halt, since transistors can only be shrunk down to a certain size and not further beyond. Thus, there is a pressing need to complement Si CMOS technology with new materials and fulfil the future computing requirements as well as the needs for diversification of applications.
Graphene and related materials offer prospects of advances in device performance at the atomic limit. They provide a possible solution to overcome the limitations of silicon technology, where the combination of layered materials with silicon chips promises to surpass the current technological limitations.
A team of researchers including Stijn Goossens and Frank Koppens, based at Graphene Flagship partner ICFO, and industrial leaders from Graphene Flagship partner IMEC and TSMC provided an in-depth and thorough review of opportunities, progress and challenges of integrating atomically thin materials with Si-based technology. They give insights on how and why layered materials could overcome current challenges posed by the existing technology and how they can enhance both device component function and performance, to boost the features of future technologies, in the areas of computational and non-computational applications.
For non-computational applications, they review the possible integration of these materials for future cameras, low power optical data communications and gas and bio-sensors. In particular, in image sensors and photodetectors, graphene and related materials could enable new vision in the infrared and terahertz range in addition to the visible range of the spectrum. These can serve for example in autonomous vehicles, security at airports and augmented reality.
For computational systems, and in particular in the field of transistors, they show how challenges such as doping, contact resistance and dielectrics/encapsulation can be diminished when integrating layered materials with Si technology. Layered materials could also improve memory and data storage devices with novel switching mechanisms for meta-insulator-metal structures, avoid sneak currents in memory arrays, or even push the performance gains of copper wire-based circuitry by adhering graphene to the ultrathin copper barrier materials and thus reduce resistance, scattering and self-heating.
The review provides a roadmap of layered material integration and CMOS technology, pinpointing the stage at which all challenges regarding growth, transfer, interface, doping, contacting, and design are currently standing today and what possible processes are expected to be resolved to achieve such goals of moving from a research laboratory environment to a pilot line for production of the first devices that combine both technologies. The layered materials-CMOS roadmap, as presented in this review, gives an exciting glimpse into the future, with pilot production expected to be just a few years from now.
Frank Koppens, Graphene Flagship Work Package Leader for Photonics and Optoelectronics and lead author of the study, says: "Now we have a clear industry-driven roadmap on layered material-silicon technologies and manufacturing. Complementing the established silicon technology with layered materials is key to combine the best of both worlds and enable a plethora of large volume and low-cost applications."
Marco Romagnoli, Graphene Flagship Work Package Leader for Wafer-Scale System Integration, comments: "This is an interesting paper complementing a previous one focused on graphene photonics for telecommunications that completes the range of applications in which graphene can be exploited for large scale production in CMOS environments. Also interesting is the type of application, in which graphene can best exploit its characteristics, from IR/THz cameras to low-power electronic switching and memories.
Andrea C. Ferrari, Science and Technology Officer of the Graphene Flagship and Chair of its Management Panel, adds: "The integration of graphene and related materials with silicon and CMOS technology is the next goal for the Flagship. For this reason, we will fund the first foundry focussed on the integration of layered materials. This work clearly spells out the vision for the transformative technology that integration will enable."
 Graphene and two-dimensional materials for silicon technology. Deji Akinwande, Cedric Huyghebaert, Ching-Hua Wang, Martha I. Serna, Stijn Goossens, Lain-Jong Li, H.-S. Philip Wong, Frank H. L. Koppens. Nature 573, 507–518 (2019).