Multi project wafer runs

The Graphene Flagship's 2D-EPL will provide five multi project wafer (MPW) runs where universities, research institutes and companies can include their designs as dies on joint wafers. The completed devices will be delivered as diced chips, wafer parts or wafers, and the pricing will be based on the area of the design on the wafer. For all the MPW runs, packaging services can be separately ordered from the MPW provider.

2D-EPL Multi Project Wafer runs

Run 1 - CLOSED

The first MPW run was mainly intended for graphene sensors and will provide the 2D-EPL an opportunity to prepare for more complex co-integrated runs later in the project. It was be delivered by AMO GmbH on October 2022 (call closed in June 2022).

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Run 2 - CLOSED

Like the first, the second MPW run was mainly intended for graphene sensors, and will be delivered by VTT Ltd in June 2023 (call closed October 2022).

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Run 3 - CLOSED

The third run will be delivered by AMO GmbH between December 2023 and January 2024 (call closed in June 2023), and is mainly intended towards electronics but can also include sensor devices (e.g. Hall sensor, but via opening on graphene is not in the scope of this run) and will be provided by AMO GmbH. The design of the device can be adjusted within the specifications.

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Run 4 - OPEN!

The fourth MPW run will be delivered by VTT Ltd by October 2024 (call closes September 2023), and will be based on graphene sensor devices on silicon CMOS wafers. The CMOS readout wafer will utilise a commercial Si CMOS process from XFAB. The CMOS design options include usage of customer designs, existing VTT designs and VTT design services. The graphene sensor post-processing utilises process modules developed in the 2D-EPL project.

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Run 5

The fifth MPW run will conditionally* be delivered by imec in September 2024 (call closes at latest in September 2023, to be confirmed) and will be offering a TMDC based transistor run for early prototyping purposes. The module will include the following steps required for TMDC based FET fabrication: TMDC transfer, TMDC patterning and contacting, gate metal deposition, gate dielectric deposition, encapsulation, via etching and metal routing for interconnections. The final definition of this MPW run will be based on the expressions of interest by the potential MPW customers.

* (if uniform wafer level transistor specs can be demonstrated in time)

More detailed MPW run descriptions coming soon!

Check back for full specifications for runs 5-7.

The EPL will be adding two additional MPW runs from partners IHP and Graphenea Semiconductor. More information to come!