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2D-PL multi-project wafer run 3

EU Funded

Graphene is an atomically thin material with extraordinary properties enabling next-generation devices and technologies. Its seamless integration with platforms such as CMOS BEOL enables enhanced functionality and efficient incorporation into existing semiconductor processes, paving the way for new innovations.

VTT uses commercially available Si CMOS readout wafers and standard semiconductor manufacturing techniques to produce CMOS integrated graphene-based devices at the wafer scale. The process flow enables graphene-based devices such as Field Effect transistors, resistors, and capacitors connected to the Si CMOS readout circuitry. VTT’s fabrication and quality control processes monitor key parameters in the runs, ensuring the customer’s devices are up to the targeted parameters. An example of the graphene FET CMOS integration by VTT is discussed in this publication.

KEY BENEFITS
  • Enabling applications such as for e-Noses, biosensor arrays, Hall sensors and IR cameras
  • Large sensor arrays with multiplexing and integrated readout
KEY FEATURES
  • 200 mm Si CMOS wafer
  • X-FAB’s XH018 process for the Si CMOS readout
  • Die size 5 mm x 5 mm
  • CMOS design options include customer designs, VTT designs and also VTT design services are available
SCHEDULE
  • 31 May 2025, Call open
  • 31 August 2025, PDK available
  • 30 November 2025: Call closes
  • 31 May 2026: Design freeze​
  • 30 November 2026: CMOS wafers ready
  • 31 March 2027: MPW run delivery target ​

PRICING

  • 45 k€ including one post-processing design and 40 dies​
  • Additional post-processing designs 3 k€ per design​
  • Additional 20 dies 3 k€
  • Pricing includes either customer’s own CMOS readout design or using VTT’s existing CMOS readout design
  • Pricing for VTT’s custom CMOS design services negotiated separately

Learn more and apply

VTT, Micronova in Espoo, Finland

About VTT

VTT Technical Research Centre of Finland Ltd is a state-owned non-profit research and technology organisation (RTO) with the aim of strengthening Finnish and European industrial competitiveness in multiple fields ranging from sustainable food and energy production to quantum computing. As an RTO VTT acts between universities and industry, bringing basic research towards industrial adaptation and helping the industry in their R&D needs. Graphene industrialisation at VTT is based on 2 600 m2 cleanroom in Micronova, Espoo, with a focus on wafer-scale CVD graphene process optimisation for electronics, photonics and sensors, including the integration on silicon CMOS for multiplexed sensor arrays. In addition to the MPW runs, VTT offers contract research, prototyping and small-scale manufacturing.

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