Graphene is an atomically thin material with extraordinary properties enabling next-generation devices and technologies. Its seamless integration with platforms such as CMOS BEOL enables enhanced functionality and efficient incorporation into existing semiconductor processes, paving the way for new innovations.
VTT uses commercially available Si CMOS readout wafers and standard semiconductor manufacturing techniques to produce CMOS integrated graphene-based devices at the wafer scale. The process flow enables graphene-based devices such as Field Effect transistors, resistors, and capacitors connected to the Si CMOS readout circuitry. VTT’s fabrication and quality control processes monitor key parameters in the runs, ensuring the customer’s devices are up to the targeted parameters. An example of the graphene FET CMOS integration by VTT is discussed in this publication.
More details on the PDK can be found here.
|
Process Step |
Layer |
Material |
|
0 |
METMID / PAD |
|
|
1 |
CMOS Via |
|
|
2 |
Via metallization |
TiW/Au |
|
3 |
Local Back Gate |
Ti/Au |
|
4 |
Gate Dielectric |
ALD Al2O3 + HfO |
|
5 a |
Bottom contact |
Ti/Au |
|
5 b |
Liquid gate |
Ti/Pt |
|
6 |
Graphene |
Monolayer CVD graphene |
|
7 |
Encapsulation |
ALD Al2O3 + HfO |
Key parameters (Encapsulated devices)
|
Parameter |
Criteria |
Value |
|
Graphene Mobility |
Mobility at gm_max |
>1000 cm²/Vs |
|
Avg. Sheet Resistance |
Doping = -1·1013 cm-2 CNP |
~1 kΩ |
|
Avg. Contact Resistance |
Doping = -1·1013 cm-2 |
~1 kΩ µm |
|
Device yield |
RDSmax < 1 MΩ |
>75 % |
|
Avg. Dirac point: |
Doping |
~ -4·1012 cm-2 |
|
Safe gate-source voltage range |
Ig_max < 10 nA |
± 10 V |
PRICE
IMPORTANT DATES
If you are interested in any of our capabilities, please contact us at miika.soikkeli@vtt.fi. Whether you are exploring a new concept or have a specific process in mind, our team can help assess your project's feasibility, discuss technical requirements, and identify the most appropriate fabrication route.
ACCESS
If interested in the VTT services, please reach out to Miika Soikkeli at miika.soikkeli@vtt.fi. The PDK will be available free of charge by signing the Design Kit License Agreement (DKLA). To join the MPW run or request custom fabrication services, the signature on the Non-Disclosure Agreement (NDA) will be necessary.
This run is now closed
The 2D-PL Support Programme lowers the obstacles for researchers and companies wanting to join our multi-project wafer (MPW) runs. Selected participants can receive a reduction of up to 50% off the MPW fee in exchange for providing feedback on the received devices in the form of a short interview with the hosting pilot line. Your feedback helps us improve future runs.
VTT Technical Research Centre of Finland Ltd is a state-owned non-profit research and technology organisation (RTO) with the aim of strengthening Finnish and European industrial competitiveness in multiple fields ranging from sustainable food and energy production to quantum computing. As an RTO VTT acts between universities and industry, bringing basic research towards industrial adaptation and helping the industry in their R&D needs. Graphene industrialisation at VTT is based on 2 600 m2 cleanroom in Micronova, Espoo, with a focus on wafer-scale CVD graphene process optimisation for electronics, photonics and sensors, including the integration on silicon CMOS for multiplexed sensor arrays. In addition to the MPW runs, VTT offers contract research, prototyping and small-scale manufacturing.
