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2D-EPL multi-project wafer run 2


EU Funded

The 2D-EPL project has launched its first multi-project wafer (MPW) run where universities, research institutes and companies can include their designs as dies on joint wafers. The second run is mainly intended for graphene sensors, and will be offered by VTT. 

Why apply?

  • Customisable chips
  • Short turn around
  • Flexible process flows
  • Direct communication channels
  • Experienced partners
  • Feasibility consulting
  • Test run for CMOS integrated devices (MPW run 4)

Important Dates

  • 1 July 2022: Call open, see specifications below
  • 30 October 2022: Call closes, design freeze
  • 1 February 2023 – 31 April 2023: MPW run

Price

  • 1300€ set price for four dies with identical design (1x1 cm²)
  • Each die more with identical design costs 250€ in addition
  • Discount of 20% for customers from countries participating in the Horizon 2020 framework

 

2D-EPL logo symbol Apply now

A schematic of the baseline process.

The offered baseline process for the second MPW run is a GFET including a top/bottom contact with an optional local or global back gate, an optional encapsulation and an optional graphene-area opening. The design of the device can be adjusted within the specifications listed below.

Specifications

Substrate

  • Silicon/SiO2
  • Basic die size : 1 x 1 cm2 (a different size can be consulted upon individual request)

Resolution

  • General design rule: 5 µm for in-layer critical dimension and over-layer alignment

Baseline Process

  • Gate module
  • Contact module
  • Graphene module
  • Encapsulation module

Characterisation

  • Raman characterisation
  • Electrical measurements

Application

  • Bio/ Gas/ Chemical sensors, Hall Sensors, Photodetectors
Learn more

Schematic of the baseline design.

VTT, Micronova in Espoo, Finland

About VTT

VTT Technical Research Centre of Finland Ltd is a state-owned non-profit research and technology organisation (RTO) with the aim of strengthening Finnish and European industrial competitiveness in multiple fields ranging from sustainable food and energy production to quantum computing. As an RTO VTT acts between universities and industry, bringing basic research towards industrial adaptation and helping the industry in their R&D needs. Graphene industrialisation at VTT is based on 2 600 m2 cleanroom in Micronova, Espoo, with a focus on wafer-scale CVD graphene process optimisation for electronics, photonics and sensors, including the integration on silicon CMOS for multiplexed sensor arrays. In addition to the MPW runs, VTT offers contract research, prototyping and small-scale manufacturing.