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A new spin on magnetic devices

Spintronics studies the spin of electrons and its associated magnetic effects. This field finds applications in logic devices, electronics and information storage, to cite a few examples. The Spintronics Work Package investigates how to integrate graphene and other layered materials into spintronic applications. Recent developments by the Graphene Flagship include new technologies for non-volatile memory – the type of computer memory that retains information even after power supplies are turned off, like hard-drives.

This year’s progress

At the beginning of Core 3, the work package created a dedicated task force to develop new combinations of layered materials and magnetic materials. Current memory technologies already exploit the latter, but graphene and related materials widen the possibilities, often demonstrating superior performance. A successful example of this integration includes the incorporation of both graphene and tungsten disulfide layers in magnetoresistive RAM (MRAM) stacks. Graphene Flagship partner imec, Belgium, supplied the wafers and partner Graphenea, Spain, transferred the graphene and other layered materials onto them. The resulting products showcased high quality and interesting magnetic properties.

Another breakthrough was the demonstration of all-electrical spin logic gates that work at room temperature. These have applications in spin communications, as well as for magnets used in reading and writing digital information. Combining graphene with layered anti-ferromagnets yielded gigantic magnetic proximity effects of up to 170 teslas.

Some of these advances rely on the creation of heterostructures, ‘sandwiches’ of different layered materials. Beyond graphene, hexagonal boron nitride and tungsten diselenide, these devices also use mono-dimensional ferromagnetic contacts, which enable the creation of lateral spin valves. These interfaces allowed unprecedented demonstrations, including room temperature spin-to-charge conversion and imprinted magnetism. The results exceed even the best predictions for Core 3. The Spintronics Work Package was remarkably productive over the past 18 months, publishing 40 papers.

The challenge now is progressing towards higher technology readiness levels (TRL). Further work on integration, validation and large-scale manufacturing will ensure we grow to TRL 4 and 5, taking graphene-enabled spintronic technologies one step closer to the market. Spintronics holds the key to low-power computing devices, from embedded memories to applications for the upcoming Internet of Things.

Upcoming challenges

We pushed the state-of-the-art in spintronics forward, thanks to research, innovation and collaboration. However, we have not yet progressed to market applications. For this reason, we established close cooperation mechanisms with the 2D-EPL, in particular imec, to accelerate the fabrication of pre-patterned wafers, readily designed to deposit layers of materials and magnetic stacks for MRAM technologies. Other efforts will focus on the validation of large-scale assembly processes, propelling our developments to TRL 5 and beyond

Work Package Leadership

Leader: Stephan Roche, ICN2, Spain
Deputy: Kevin Garello, CEA, France 

Division Leadership

Leader: Stephan Roche, ICN2, Spain
Deputy: Alberto Morpurgo, Université de Geneve, Switzerland

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