Multi project wafer runs
The Graphene Flagship's 2D-EPL will provide five multi project wafer (MPW) runs where universities, research institutes and companies can include their designs as dies on joint wafers. The completed devices will be delivered as diced chips, wafer parts or wafers, and the pricing will be based on the area of the design on the wafer. For all the MPW runs, packaging services can be separately ordered from the MPW provider.
Upcoming Multi Project Wafer runs
The first MPW run is mainly intended for graphene sensors and will provide the 2D-EPL an opportunity to prepare for more complex co-integrated runs later in the project. It will be delivered by AMO GmbH on October 2022 (call closes in June 2022).
Like the first, the second MPW run is mainly intended for graphene sensors, and will be delivered by VTT Ltd on April 2023 (call closes October 2022).
The third run will be delivered by AMO GmbH between December 2023 and January 2024 (call closes in June 2023), and will be directed towards electronics but can also include sensor devices; the final definition of this MPW run will be based on expressions of interest by the potential MPW customers.
The fourth MPW run will be delivered by VTT Ltd on April 2024 (call closes October 2023), and will be based on graphene sensor devices on silicon CMOS wafers. The CMOS wafer will include options for sensor array multiplexing, standard referencing elements designed for graphene FET-type sensors and possibly for MEMS type sensors. PDK will include the basic design elements for the referencing and readout structures on silicon CMOS and interfacing between the silicon CMOS and the graphene devices, but it will also be possible to include the CMOS design from the MPW customer. The final definition of this MPW run will be done based on expressions of interest by the potential MPW customers. Only chips will be available.
The fifth MPW run will conditionally* be delivered by imec in September 2024 (call closes at latest in September 2023, to be confirmed) and will be offering a TMDC based transistor run for early prototyping purposes. The module will include the following steps required for TMDC based FET fabrication: TMDC transfer, TMDC patterning and contacting, gate metal deposition, gate dielectric deposition, encapsulation, via etching and metal routing for interconnections. The final definition of this MPW run will be based on the expressions of interest by the potential MPW customers.
* (if uniform wafer level transistor specs can be demonstrated in time)
More detailed MPW run descriptions coming soon!
Check back for full specifications for runs 3-5.
The EPL will be adding two additional MPW runs from partners IHP and Graphenea Semiconductor. More information to come!