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Wafer-Scale System Integration

Silicon: the perfect pairing for graphene

All the exciting applications for graphene in electronics and optoelectronics heavily rely on a successful integration with traditional silicon devices. Therefore, the Wafer-scale Integration Work Package develops the processes to incorporate graphene and related materials into silicon foundries’ manufacturing pipelines. Our work is key to attaining the Graphene Flagship’s primary goal, taking graphene from the lab… to the fab!

This year’s progress

In the world of electronics, wafers are thin slices of semiconductor materials – usually crystalline silicon. Our work package optimises the fabrication process to cover silicon with layers of graphene and related materials, to achieve different properties for a variety of applications. This requires the optimisation of different steps: growth of graphene, transfer and encapsulation. In the past year, we improved all these techniques to achieve record-breaking results in terms of uniformity and carrier mobility, two factors directly correlated to the quality of graphene-enabled devices.

We demonstrated a wafer-scale method for building single crystal matrices on silicon and silicon nitride. These structures have applications in electronics, optoelectronics and photonics; among these optical- and electro-absorption modulators and ultrafast detectors. The reproducibility of this approach is outstanding. We also develop customised tools for graphene-based wafer scale platforms, including transfer and delamination devices.

Thanks to the collaborations between academia and industry, fostered by the project, most of the processes developed within our work package have already reached the European market. For example, Graphene Flagship partner Graphenea, Spain, commercialises wafer-scale graphene field effect transistors (GFET). Graphene Flagship partners Aixtron, Germany, and DTU, Denmark, have developed an innovative roll-to-roll system to deposit graphene on 100mm-wide flexible substrates, now close to commercialisation.

Overall, the Wafer-scale Integration Work Package has consistently increased the technology readiness level (TRL) of different technologies to manufacture graphene-enabled devices in a reproducible and reliable manner. Our work paves the way to applications like high-performance photonic circuits for telecom and datacom and innovative image sensors for multispectral applications.

Upcoming challenges

The Wafer-scale Integration Work Package strives to improve current processes even further. Our researchers will optimise all the operations required for the integration of graphene and silicon. We will work on the encapsulation of graphene, as the preservation of this one-atom-thick material throughout the different fabrication steps is key. Graphene must keep its excellent properties to guarantee applications in telecom, datacom, sensors and many more.

Work Package Leadership


Leader: Marco Romagnoli, CNIT, Italy
Deputy: Amaia Zurutuza, Graphenea Semiconductor, Spain

Division Leadership


Leader: Marco Romagnoli, CNIT, Italy
Deputy: Maria Smolander, VTT Technical Research Centre of Finland Ltd

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